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| a FEATURES Allows Safe Board Insertion and Removal from a Live -48 V Backplane Typically Operates from -36 V to -80 V Tolerates Transients up to -200 V (Limited by External Components) Accurate Programmable Linear Current Limit for In-Rush Control and Short Circuit Protection Programmable Timeout in Current Limit Limited Consecutive Retry: Auto-Restart after Current Limit Timeout Shutdown after Seven Consecutive Auto Restarts Provides Immunity from Step Induced Current Spikes Default Timing Provided with no TIMER Capacitor Single Pin Undervoltage/Overvoltage Detection Programmable Operating Voltage Window Programmable Undervoltage/Overvoltage Time Filter Small 6-Lead SOT-23 Package APPLICATIONS Central Office Switching -48 V Distributed Power Systems Negative Power Supply Control Hot Board Insertion Electronic Circuit Breaker High Availability Servers Programmable Current Limiting Circuit -48 V Power Supply Modules 0V VDD -48 V Hot Swap Controller ADM1070 FUNCTIONAL BLOCK DIAGRAM RDROP 16k VIN CLOAD VOUT R1 12V VCC AND REFERENCE GENERATOR VCC VREF UV/OV OVER-UNDER VOLTAGE DETECTION CIRCUIT 100mV EN VIN 45 A Q1 GATE R2 FAULT TIMER AND CONTROL TIMER OSCILLATOR ( )* SENSE RSENSE ADM1070 -48V VEE *OPTIONAL TIMER CAPACITOR VEE GENERAL DESCRIPTION The ADM1070 is a negative voltage hot swap controller that allows a board to be safely inserted and removed from a live -48 V backplane. The part achieves this by providing robust current limiting, protection against transient and nontransient short circuits and overvoltage and undervoltage conditions. The ADM1070 typically operates from a negative voltage of up to -80 V and can tolerate transient voltages of up to -200 V. In-rush current is limited to a programmable value by controlling the gate drive of an external N-channel FET. The current limit can be controlled by the choice of the sense resistor, RSENSE. Added control of the in-rush current is provided by an on-chip timer that uses pulsewidth modulation to allow the maximum current to flow for only 3% of the time. An autorestart occurs after a current limit timeout. After seven successive autorestarts, the fault will be latched and the part goes into shutdown with the result that the external FET is disabled until the power is reset. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. The ADM1070 also features single-pin undervoltage and overvoltage detection. The FET is turned off if a nontransient voltage less than the undervoltage threshold, typically -36 V, or greater than the overvoltage threshold, typically -77 V, is detected on the UV/OV Pin. The operating voltage window of the ADM1070 is programmable and is determined by the ratio R1/R2. Time filtering on the undervoltage and overvoltage detection and current limiting is programmable via the TIMER Pin. An external capacitor connected between the TIMER Pin and VEE determines the undervoltage/overvoltage time filter and the timeout in current limit. If the pin is tied to VEE, the time filter values and the current limit timeout revert to default figures. The ADM1070 is fabricated using BiCMOS technology for minimal power consumption. The part is available in a small 6-Lead SOT-23 package. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002 ADM1070-SPECIFICATIONS Parameter BOARD SUPPLY (not connected directly to device) Maximum Voltage Range Typical Operating Voltage Range VIN PIN--SHUNT REGULATOR Operating Supply Voltage Range, VSS Quiescent Supply Current, ISS Maximum Shunt Supply Voltage, VSS Undervoltage Lockout, VLKO UV/OV PIN--UNDERVOLTAGE AND OVERVOLTAGE DETECTION Undervoltage Falling Threshold, VUVF Undervoltage Rising Threshold, VUVR Undervoltage Hysteresis, VUVH Overvoltage Falling Threshold, VOVF Overvoltage Rising Threshold, VOVR Overvoltage Hysteresis VOVH Power-On Reset Delay, tPOR (VDD = 0 V, VEE = -48 V, RDROP = 16 k , TA = -40 C to +85 C, unless otherwise noted.) Typ Max Unit Test Conditions Min -200 -77 11.5 0.4 7 -48 -48 12.3 0.85 12.5 8.5 -20 -36 13 1.3 14 10.5 V V V mA V V Limited by Voltage Capability of External Components* RDROP = 16 k, R1/R2 = 40* ISS = 1.5 mA to 4.25 mA VSS = 11.5 V ISS = 20 mA 0.81 0.86 1.85 1.89 1.10 0.90 0.86 0.91 45 1.93 1.97 -45 1.70 1.21 0.91 0.96 2.01 2.05 2.30 1.51 V V mV V V mV ms ms TIMER Pin Tied to VEE (VUVR < UV/OV < VOVF) CTIMER = 470 pF (VUVR < UV/OV < VOVF) TIMER Pin Tied to VEE (VUVR < UV/OV < VOVF) CTIMER = 470 pF (VUVR < UV/OV < VOVF)* Voltage Fault Filter Time (UV/OV Out of Voltage Window), tFLT 1.10 0.90 1.70 1.21 2.30 1.51 1.0 ms ms A V mV A mA k k mV mV mV mV mV mV mV Input Current, IVMON GATE PIN--FET DRIVER Maximum Gate Voltage, VGMAX Minimum Gate Voltage, VGMIN Pull-Up Current, IGUP Pull-Down Current, IGDP Hold-off Impedance, RGOFF SENSE PIN--CURRENT SENSE Analog Current Limit Voltage (Rising),VLIM Circuit Breaker Limit Voltage (Rising) Circuit Breaker Limit Voltage (Rising) (With Respect to VLIM), VLIMITON Circuit Breaker Limit Voltage (Falling) Circuit Breaker Limit Voltage (Falling) (With Respect to VLIM), VLIMITOFF Fast Current Limit Voltage Fast Current Limit Voltage (With Respect to VLIM) Control Loop Transconductance, (dIGATE/dVSENSE) Maximum Current Limit On Time, tLIMITON 11 0 -20 10 12 -40 30 13 50 -55 10 30 IGATE = -1 A IGATE = 1 A VGATE = 0 V to 9 V, VSENSE = 0 VGATE = VSS VGATE < 2 V, VSS > 11 V VGATE < 2 V, VSS > 2 V IGATE = 0 A to -15 A 90 75 100 88 -12 79 -21 126 26 2.75 14 9.9 450 320 3 7 -2- 110 100 60 95 107 145 1.5 10 7.4 4 18 12.4 580 400 A/mV IGATE < ms ms ms ms % 30 A, TA = 25C Current Limit PWM Off Time 320 240 Current Limit PWM Duty Cycle Number of Consecutive PWM Retry Cycles TIMER Pin Tied to VEE (VUVR < UV/OV < VOVF) CTIMER = 470 pF (VUVR < UV/OV < VOVF)* TIMER Pin Tied to VEE (VUVR < UV/OV < VOVF)* CTIMER = 470 pF (VUVR < UV/OV < VOVF)* (Typical Only) (Typical Only) REV. 0 ADM1070 Parameter SENSE PIN--CURRENT SENSE (continued) Continuous Short Circuit Time before Latched Shutdown, tSHORT Operating Sense Voltage Range, VSOP Input Current, ISENSE TIMER PIN--TIMING CONTROL Internal Oscillator Default Frequency, fTIMERINT (Not Seen at Pin) External/Internal Selection Threshold, VTIMERTHEI High Trip Threshold, VTIMERTHH Low Trip Threshold, VTIMERTHL Pull-Down Current, ITIMERDN Pull-Up Current, ITIMERUP Start-Up Current, ITIMERSTART *Not production tested. Guaranteed by design. Specifications subject to change without notice. Min 2100 1500 0 -500 Typ 2800 2000 0.11 Max 3500 2500 Unit ms ms V A kHz Test Conditions TIMER Pin Tied to VEE (VUVR < UV/OV < VOVF) CTIMER = 470 pF (VUVR < UV/OV < VOVF)* VSENSE = -2 V to +2 V TIMER Pin Tied to VEE +500 9.0 0.3 3.0 1.2 15 -15 -12 0.45 3.5 1.5 24 -24 -19 0.6 4.0 1.8 31 -31 -26 V V V A A A VTIMER > VTIMERTHH VTIMERTHEI < VTIMER < VTIMERTHL VTIMER < VTIMERTHEI ABSOLUTE MAXIMUM RATINGS* (All voltages referred to V EE, unless otherwise noted. T A = 25C, unless otherwise noted.) THERMAL CHARACTERISTICS 6-Lead SOT-23 Package: JA = 226.6C/W, JC = 91.99C/W Supply Voltage (VDD-VEE) . . . . . . . . . . . . . -0.3 V to -200.0 V Maximum Shunt Supply Voltage, VSS . . . . . . . . . . . . . . . 16 V SENSE Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2 V to +16 V GATE Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +16 V UV/OV Pin . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +15 V TIMER Pin . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +10 V Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125C Temperature Range . . . . . . . . . . . . . . . . . . . . -40C to +85C Continuous Power Dissipation . . . . . . . . . . . . . . . . . 282 mW Storage Temperature Range . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300C *This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. ORDERING GUIDE Model ADM1070ART Temperature Range -40C to +85C Package Description 6-Lead Package Option RT-6 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADM1070 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. 0 -3- ADM1070 PIN CONFIGURATION SENSE 1 6 GATE UV/OV TIMER ADM1070ART VEE 2 TOP VIEW (Not to Scale) 5 VIN 3 4 PIN FUNCTION DESCRIPTION Pin No. 1 Mnemonic SENSE Function Connection to External FET Source Voltage. A sense resistor is connected in the supply path between the SENSE Pin and VEE, and the voltage across this resistor is monitored to detect current faults. This voltage is fed as an input to the linear current regulator. When it reaches 100 mV for a specified period, tON, the regulator reduces the gate voltage and drives the FET as a linear pass device. If current monitoring is not required, this feature can be turned off by shorting the SENSE Pin and VEE together. Device Negative Supply Voltage. This pin should be connected to the lower potential of the power supply. Shunt Regulated On-Chip Supply, Nominally VEE + 12.3 V. This pin should be current fed through a dropper resistor that is connected to the higher potential of the power supply inputs. Allows User Control over Timing Functions by Determining Frequency of Oscillator. Frequency set by connecting external capacitor to VEE. Tying pin directly to VEE causes oscillator to default to internally set value. Input Pin for Overvoltage and Undervoltage Detection Circuitry. The voltage appearing on the UV/OV Pin is proportional to board supply and is determined by external resistors. When the voltage on UV/OV falls below the undervoltage threshold of 0.86 V, the GATE Pin is driven low. When the voltage appearing at the UV/OV Pin rises above the overvoltage threshold of 1.97 V, the GATE Pin is also driven low. If the external resistor ratio of R1/R2 = 40 is used, then this gives an operating range of -36 V to -77 V. Output to External FET Gate Drive. Controlled by linear current regulator. The gate is driven low if an overvoltage or undervoltage fault occurs or if a current fault lasts for longer than the time, tON. When in linear regulation, the GATE Pin voltage is controlled as part of the servo loop. No external compensation is required. When the FET is fully enhanced and the load capacitance has been charged, the GATE Pin reaches a high level of typically 12 V. 2 3 4 VEE VIN TIMER 5 UV/OV 6 GATE -4- REV. 0 Typical Performance Characteristics- ADM1070 2.0 1.8 14.5 14.0 1.6 1.4 13.5 13.0 12.5 12.0 11.5 IIN - mA 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -35 -20 -5 10 25 40 TEMPERATURE - C 55 70 85 VZ - V 11.0 -45 -35 -25 -15 -5 5 15 25 35 45 TEMPERATURE - C 55 65 75 85 TPC 1. IIN vs. Temperature TPC 4. VZ vs. Temperature 1000 12 11 100 10 VLKO - V +85 C 1 +25 C 0.1 0 2 4 6 8 VIN - V 10 12 14 16 -40 C IIN - mA 10 9 8 7 6 -50 -35 -20 -5 10 25 40 TEMPERATURE - C 55 70 85 TPC 2. IIN vs. VIN TPC 5. Undervoltage Lockout, VLKO vs. Temperature 10 9 8 7 VCB - mV RZ - V 100 95 90 85 80 FALLING 75 70 65 60 -50 RISING 6 5 4 3 2 -45 -35 -25 -15 -5 5 15 25 35 45 TEMPERATURE - C 55 65 75 85 -35 -20 -5 10 25 40 TEMPERATURE - C 55 70 85 TPC 3. RZ vs. Temperature TPC 6. Circuit Breaker Current Limit Voltage, VCB vs. Temperature REV. 0 -5- ADM1070 120 115 50 60 110 40 IGATE - mA VACL - mV 105 100 95 30 20 90 10 85 80 -50 0 -50 -35 -20 -5 10 25 40 TEMPERATURE - C 55 70 85 -35 -20 -5 10 25 40 TEMPERATURE - C 55 70 85 TPC 7. Analog Current Limit Voltage, VACL vs. Temperature TPC 10. IGATE (FCL, Sink) vs. Temperature (VGATE = 9 V) 150 145 140 14.0 13.5 13.0 135 VFCL - mV VGATE - V 130 125 120 115 12.5 12.0 11.5 11.0 110 105 100 -50 -35 -20 -5 10 25 40 TEMPERATURE - C 55 70 85 10.5 10.0 -50 -35 -20 -5 10 25 40 TEMPERATURE - C 55 70 85 TPC 8. Fast Current Limit Voltage, VFCL vs. Temperature TPC 11. VGATE vs. Temperature 60 50 55 40 50 VGATEL - mV IGATE - A 30 45 20 40 10 35 30 -50 -35 -10 5 25 40 TEMPERATURE - C 55 70 85 0 -40 -30 -20 -10 0 10 20 30 40 50 TEMPERATURE - C 60 70 80 90 TPC 9. IGATE (Source) vs. Temperature TPC 12. VGATEL vs. Temperature -6- REV. 0 ADM1070 50 45 40 35 2.00 OV HIGH 2.05 IGATE - mA 30 25 20 15 10 5 0 0 1 2 3 4 5 6 7 8 9 10 11 12 VOV - V 1.95 OV LOW 1.90 1.85 1.80 -50 -35 -20 VGATE - V -5 10 25 40 TEMPERATURE - C 55 70 85 TPC 13. IGATE vs. VGATE TPC 16. OV Threshold vs. Temperature 4.0 HIGH 3.5 3.0 10 9 8 TIMER THRESHOLD - V 7 A ISENSE - 2.5 2.0 1.5 LOW 1.0 6 5 4 3 2 0.5 0 -50 1 -35 -20 -5 10 25 40 TEMPERATURE - C 55 70 85 0 -50 -35 -20 -5 10 25 40 TEMPERATURE - C 55 70 85 TPC 14. High and Low Timer Thresholds vs. Temperature TPC 17. ISENSE vs. Temperature (VSENSE = 50 mV) 1.00 -60 -40 0.95 UV HIGH -20 -2.0 -1.6 -1.2 -0.8 0 -0.4 0 0.4 0.8 1.2 1.6 2.0 0.90 I SENSE - A 70 85 VUV - V 20 40 60 0.85 UV LOW 0.80 80 100 0.75 -50 -35 -20 -5 10 25 40 TEMPERATURE - C 55 120 VSENSE - VEE TPC 15. UV Threshold vs. Temperature TPC 18. ISENSE vs. (VSENSE - VEE) REV. 0 -7- ADM1070 4.0 3.5 3.0 3.5 TSHORT - SEC 5.0 4.5 4.0 TPOR - ms 2.5 2.0 1.5 1.0 0.5 0 -50 TIMER -> 470pF TIMER -> VEE 3.0 2.5 2.0 TIMER -> VEE TIMER -> 470pF 1.5 1.0 0.5 -35 -20 -5 10 25 40 TEMPERATURE - C 55 70 85 0 -50 -35 -20 -5 10 25 40 TEMPERATURE - C 55 70 85 TPC 19. POR Delay vs. Temperature TPC 22. Continuous Short Circuit Time before Shutdown vs. Temperature 4.0 3.5 3.0 5.0 4.5 4.0 3.5 2.5 TFLT - ms 2.0 1.5 PWM - % 3.0 2.5 2.0 1.5 TIMER -> VEE - 1.0 0.5 0 -50 TIMER -> 470pF 1.0 0.5 -35 -20 -5 10 25 40 TEMPERATURE - C 55 70 85 0 -50 -35 -20 -5 10 25 40 TEMPERATURE - C 55 70 85 TPC 20. Voltage Fault Filter Time vs. Temperature TPC 23. Current Limit PWM vs. Temperature 20 18 16 14 TON - ms TIMER -> VEE 12 10 TIMER -> 470pF 8 6 4 2 0 -50 -35 -20 -5 10 25 40 TEMPERATURE - C 55 70 85 TPC 21. Maximum Current Limit On Time vs. Temperature -8- REV. 0 ADM1070 FUNCTIONAL DESCRIPTION HOT CIRCUIT INSERTION Inserting circuit boards into a live -48 V backplane can cause large transient currents to be drawn as the board capacitance charges up. These transient currents can cause glitches on the system power supply and can permanently damage components on the board. The ADM1070 is designed to control the manner in which a board's supply voltage is applied so that harmful transient currents do not occur and the board can be safely inserted or removed from a live backplane. Undervoltage, overvoltage, and overcurrent protection are other features of the part. The ADM1070 ensures that the input voltage is stable and within tolerance before being applied to the dc-to-dc converter, which generates the low voltage levels required to power the on-board logic. One such converter is the Artesyn EXQ50. Go to www.artesyn.com for more information. PLUG-IN BOARD ARTESYN EXQ50 0V R1 LIVE BACKPLANE R2 -48V RSENSE FET VIN- VIN+ Figure 2 shows how a plug-in module containing the ADM1070 makes connection to the backplane supply. When the board is inserted, the -48 V and 0 V lines connect. This powers up the device with the voltage on VIN exceeding VLKO. When the voltage at the UV/OV Pin exceeds undervoltage rising threshold (VUVR) of 0.91 V, it is now inside the operating voltage window. It must stay inside this window for the duration of the power-on reset delay time, tPOR, which is dependent on the value of CT. When the device detects that the supply voltage is valid, it ramps up the gate voltage until the FET turns on and the load current increases. The ADM1070 monitors the level of the current flowing through the FET by sensing the voltage across the external sense resistor, RSENSE. When the sense voltage reaches 100 mV, the GATE Pin is actively controlled, limiting the load current. In this way, the maximum current permitted to flow through the load is set by the choice of RSENSE. If a change in the level of the supply voltage causes UV/OV to fall below the undervoltage falling threshold of VUVF, or rise above the overvoltage rising threshold of VOVR, then the gate drive will be disabled. BOARD REMOVAL VOUT+ ADM1070 CLOAD VOUT- TRIM If the board is removed from a card cage, the voltage at the UV/OV pin falls to zero (i.e., outside operating range) and the gate drive is deasserted, turning off the FET. CONTROLLING THE CURRENT Figure 1. Topology INITIAL STARTUP The ADM1070 hot swap controller normally resides on a removable circuit board and controls the manner in which power is applied to the board upon connection. This is achieved using a FET, Q1, in the power path. By controlling the gate voltage of the FET, the surge of current to charge load capacitance can be limited to a safe value when the board makes connection. Note that the ADM1070 can also reside on the backplane itself, and perform the same function from there. 0V RDROP 16k CLOAD VOUT The ADM1070 features a current limiting function that protects against short circuits or excessive supply currents. The flow of current through the load is monitored by measuring the voltage across the sense resistor, which is connected between the SENSE and VEE Pins. There are three different types of protection offered: 1. If the voltage across the sense resistor exceeds the circuit breaker limit voltage of 88 mV (rising) for the current limit on time (tLIMITON), then a current fault has occurred and the PWM cycle begins. The FET current is linearly controlled at a maximum of 100 mV/RSENSE (via the gate drive) during tLIMITON (see next section). The gate is then disabled for the duration tOFF. This PWM ratio, which will always be 3%, is given by tON/tOFF. A unique feature of the ADM1070 is the limited consecutive retry function. An internal fault counter keeps track of the number of successive PWM cycles that occur. The fault counter is incremented after every fault is detected. If the ADM1070 detects seven consecutive current faults, it is apparent that the fault is not a temporary one and the device latches itself off. The fault counter is cleared if a new tON timeout does not occur within 2 tOFF of the previous tLIMITON timeout. VIN R1 LIVE BACKPLANE ADM1070 UV/OV GATE Q1 SENSE TMER R2 VEE RSENSE -48V Figure 2. Circuit Board Connection REV. 0 -9- ADM1070 2. If a voltage between the SENSE and VEE Pins increases to 100 mV (the analog current limit voltage) during tLIMITON, then the ADM1070 takes action to reduce this current to a safer level. The internal analog current limit loop dynamically adjusts the gate drive, keeping the load current at the 100 mV/RSENSE level. The FET now acts as a current source, limiting the load current to the level set by the value of the sense resistor. The sense voltage is also above the circuit breaker limit voltage, so the limited consecutive retry function is still operational. If the current fault is not cleared (sense resistor voltage brought below 79 mV) after seven consecutive faults, then the device is latched off. 3. If a serious short circuit occurs on the load side, the -48 V supply can cause massive currents to flow very quickly. Because of this, the gate voltage must be reduced quickly to prevent a catastrophic failure. If the ADM1070 detects a voltage greater than the fast current limit voltage (126 mV) across the sense resistor, it is apparent that a serious short circuit is present and the load current must be reduced as quickly as possible. The fast current limit loop takes over and pulls gate low much faster than in the previous case. SENSE RESISTOR SHUNT REGULATOR A shunt regulator shunts the ADM1070 V IN Pin. Power is derived from the -48 V supply through the combination of an internal Zener diode and an external shunt resistor, R DROP. Table II shows the operational voltage range and power dissipation for different values of RDROP. Note that 16 k is the default value for RDROP. Table II. Minimum and Maximum Allowable Operating Voltages for Different Values of R DROP RDROP 10 k (0.25 W) 12 k 14 k 16 k 18 k 20 k 22 k 10 k (0.5 W) 12 k 14 k 16 k 18 k 20 k 22 k Min Allowable VDD Voltage (V) 26 28.6 31.2 33.8 36.4 39 41.6 26 28.6 31.2 33.8 36.4 39 41.6 Max Allowable VDD Voltage (V) 61 65.8 70.2 74.2 78.1 81.7 85.2 81.7 88.5 94.7 100.4 105.9 111 115.9 PDROP @ 48 V (W) 0.13 0.11 0.09 0.08 0.07 0.065 0.06 0.13 0.11 0.09 0.08 0.07 0.065 0.06 The ADM1070's current limiting function can operate at different current levels. The sense resistor is inserted between the VEE and sense pins, and a current fault occurs whenever the voltage across the sense resistor is greater than 100 mV for longer than the on time, tLIMITON. The current limit is determined by selection of the sense resistor, R SENSE. Table I shows how the maximum allowable load current (I LOAD(MAX)) and the minimum and maximum in-rush currents (ILIMIT(MIN)) and ILIMIT(MAX)) are related to the value of RSENSE. Table I. ILOAD(MAX), ILIMIT(MIN), and ILIMIT(MAX) for Different Values of R SENSE INTERNAL UNDERVOLTAGE LOCKOUT The VIN Pin is monitored for undervoltage lockout. When the voltage at VIN is above 8.5 V (VLKO), the device is enabled. If this voltage drops below 8.5 V, the device is disabled and gate is pulled low. Note that this is unrelated to the undervoltage and overvoltage functions performed at the UV/OV Pin. TIMER RSENSE (m ) 5 10 15 18 22 33 47 51 68 75 90 ILOAD(MAX) (A) 12.0 6.0 4.0 3.3 2.7 1.8 1.3 1.2 0.9 0.8 0.7 ILIMIT(MIN) (A) 18.0 9.0 6.0 5.0 4.1 2.7 1.9 1.7 1.3 1.2 1.0 ILIMIT(MAX) (A) 22.0 11.0 7.3 6.1 5.0 3.3 2.3 2.2 1.6 1.5 1.2 The TIMER Pin on the ADM1070 gives the user control over the timing functions on the part. By connecting an external capacitor between the TIMER Pin and VEE, the user can set the UV/OV glitch filter time, tFLT, the power-on reset delay time, tPOR, the maximum current on time, tON, the current limit time out, tOFF, and the continuous short circuit time before latched shutdown, tSHORT (see Table III). Note that all times are scaled relative to each other and cannot be altered individually (without changing the other times). The default values for these times are selected by tying the TIMER Pin directly to VEE. Table III. Timer Capacitor Values and Timing Values CTIMER (pF) 220 330 470 Tied to VEE 680 1000 2200 tFLT (ms) 0.58 0.85 1.21 1.55 1.74 2.54 5.64 tPOR (ms) 0.58 0.85 1.21 1.55 1.74 2.54 5.64 tLIMITON (ms) 4.8 7.1 9.9 12.8 14.2 20.8 46.2 tPWMOFF (ms) 150 230 320 410 450 660 1465 tSHORT (ms) 1000 1400 2000 2600 2800 4100 9113 -10- REV. 0 ADM1070 UNDERVOLTAGE/OVERVOLTAGE DETECTION Voltage Divider: VUV/OV = VSS(R2/(R1 + R2)) For R2 = 1 k: VSS = VUV/OV(R1 + 1) + The ADM1070 incorporates single-pin overvoltage and undervoltage detection with a programmable operating voltage window. When the voltage on the UV/OV pin rises above the OV rising threshold or falls below the UV falling threshold, a fault signal is generated that disables the linear current regulator and results in the GATE Pin being pulled low. The voltage fault signal is time filtered so that faults of duration less than the UV/ OV glitch filter time, tFLT, do not force the gate drive low (tFLT is set by the choice of external capacitor CT, see Table III). The filter operates only on the "faulting" edge (i.e., on a high to low transition on the undervoltage monitor and on a low to high transition on the overvoltage monitor). The analog comparators have some hysteresis to provide smooth switching of the comparator inputs. If the voltage on UV/OV goes out of range (i.e., below 0.86 V or above 1.97 V) gate is pulled low. If the UV/OV voltage subsequently re-enters the operating voltage window, the ADM1070 will restore the gate drive. The overvoltage and undervoltage thresholds are: UV turning on = 0.91 V UV turning off = 0.86 V OV turning on = 1.97 V OV turning off = 1.93 V The undervoltage/overvoltage levels are determined by selection of the resistor ratio R1/R2, (see Table I). These two resistors form a resistor divider that generates the voltage; at the UV/OV Pin, which is proportional to the supply voltage. By choosing this ratio carefully, the ADM1070 can be programmed to apply the supply voltage to the load only when it is within specific thresholds. For example, for R1 = 39 k and R2 = 1 k the typical operating range is 36.4 V to 76.8 V. The undervoltage and overvoltage shutdown thresholds are 34.4 V and 77.2 V for this resistor ratio. 1% resistors should be used to maintain the accuracy of these threshold levels. And for R1 = 39 k: VSS = 40 VUV/OV VSS R1 + R2 V UV/OV - - Operating Range: UV => 40(0.91) = 36.4 V OV => 40(1.93) = 77.2 V Figure 3. Voltage Divider UV/OV Shutdown Levels: UV => 40(0.86) = 34.4 V OV => 40(1.97) = 78.8 V 120 100 OPERATING VOLTAGE - V 80 60 40 20 0 30 33 36 R1 - k 39 43 (FOR R2 = 1k ) 47 51 Figure 4. Operating Voltage Window vs. Resistance Ratio Table IV. Resistance Ratios and Operating Voltage Windows Resistor Ratio R1 (for R2 = 1 k ) k 30 33 36 39 43 47 51 Undervoltage VUV (Falling) V 26.7 29.2 31.8 34.4 37.8 41.3 44.7 VUV (Rising) V 28.2 31.0 33.7 36.4 40.0 43.7 46.4 Overvoltage VOV (Falling) V 59.8 65.6 71.4 77.2 84.9 92.6 100.4 VOV (Rising) V 61.0 67.0 72.9 78.8 86.7 94.6 102.4 REV. 0 -11- ADM1070 FUNCTIONALITY AND TIMING Live Insertion OVERVOLTAGE AND UNDERVOLTAGE The timing waveforms associated with the live insertion of a plug-in board using the ADM1070 are shown in the following figures. When the board connects the GND-VEE potential climbs to 48 V. As this voltage is applied, the voltage at the VIN Pin ramps above the undervoltage lockout (VLKO) of 8.5 V to a constant 12.3 V and is held at this level with the shunt resistor and external resistor combination at the VIN Pin. When UV/OV crosses the undervoltage rising threshold of 0.91 V, it is now inside the operating voltage window and the -48 V supply must be applied to the load. After a time delay, tPOR, the ADM1070 begins to ramp up the gate drive. When the voltage on the SENSE Pin reaches 100 mV (the analog current limit) the gate drive is held constant. When the board capacitance is fully charged, the sense voltage begins to drop below the analog current limit voltage and the gate voltage is free to ramp up further. The gate voltage eventually reaches its maximum value of 12.3 V (as set by VIN). The waveforms for an overvoltage glitch are shown below. When UV/OV glitches above the overvoltage rising threshold of 1.97 V, an overvoltage condition is detected and the gate voltage is pulled low. UV/OV begins to drop a back toward the operating voltage window and the gate drive is restored when the overvoltage falling threshold of 1.93 V is reached. Figure 7 illustrates the ADM1070's operation in an overvoltage situation. GATE T T SENSE VUV/OV GND-VEE CH1 CH3 10.00V 1.00V CH2 100mV M 200 s CH3 1.96V VIN V LKO Figure 7. Timing Waveforms Associated with an Overvoltage Glitch V UVR UV/OV GATE SENSE An undervoltage glitch is dealt with in a similar way. When VUV/OV falls below the undervoltage falling threshold of 0.86 V, the gate voltage is pulled low. If UO/UV subsequently rises back above the undervoltage rising threshold of 0.91 V, then the gate voltage is restored. Figure 8 illustrates the ADM1070's operation in an undervoltage situation. VOUT GATE t POR Figure 5. Timing Waveforms Associated with a Live Insertion Event SENSE GATE T VUV/OV SENSE T CH1 CH3 VOUT 10.0V 1.00V CH2 100mV M 200ms Figure 8. Timing Waveforms Associated with an Undervoltage Glitch CH1 5.00V CH3 10.00V CH2 100mV M 500 s CH1 2.8V Figure 6. Start-Up Sequence -12- REV. 0 ADM1070 CURRENT FAULT PLOTS Some timing waveforms associated with current over faults are shown in the following figures. Figure 9 shows how a current glitch (of approximately 500 s) is dealt with when the output is shorted after power-up. The gate voltage is at a constant 12.3 V before the glitch occurs. When the short circuit occurs, the sense voltage rises sharply as the load current ramps up quickly. When the sense voltage reaches 100 mV (VACL ), the ADM1070 reduces the gate voltage to stop the load current from increasing any further. When VSENSE drops back below VACL, the gate voltage is increased again. GATE T Figure 11 shows a current fault on a wider timebase. The first spike on the sense line represents the first current fault. The sense voltage is allowed to ramp up to 100 mV before the gate voltage is reduced to compensate. The gate and sense voltages remain at these levels until the tON time has expired. A current fault is then registered and the gate voltage, and therefore the sense voltage, are then both held low for the time period tOFF. Note that the PWM ratio (tON/tOFF) is equal to 3%. The cycle then restarts and the sense voltage is free to ramp up to 100 mV again (it will if the fault is still present). This cycle repeats itself a total of seven times. Figure 12 shows the seven consecutive faults occurring on an even wider timebase. If the ADM1070 detects seven consecutive current faults, the part then latches off (after a total time tSHORT). T SENSE tOFF tON GATE T VOUT CH1 10.00V CH3 20.00V CH2 100mV M 500 s CH2 34mV SENSE Figure 9. Timing Waveforms Associated with a Current Glitch The plots shown illustrate the operation of the ADM1070's unique limited consecutive retry function. Figure 10 highlights what happens when a current fault occurs for more than 14 ms (default tLIMITON when TIMER Pin tied to VEE) and a current fault is registered. In this case, gate is previously low and the part is being powered up into a current fault situation (shorted load). When power is applied, gate is allowed to ramp until sense reaches 100 mV. gate is then held constant to keep sense at this level. After tON, the PWM cycle begins and gate is reduced to zero. CH1 5.00V CH3 1.00V CH2 100mV M 100ms Figure 11. Illustration of the PWM Ratio (tON/tOFF) t SHORT GATE 14ms SENSE GATE CH1 5.00V CH3 1.00V CH2 100mV M 100ms Figure 12. Illustration of the Limited Consecutive Retry Function (Seven Retries and Latch Off) SENSE CH1 5.00V CH2 100mV M 5.00 s CH1 1.4V Figure 10. Timing Waveforms Associated with a Current Fault REV. 0 -13- ADM1070 Figure 13 shows the behavior of ADM1070 when a temporary current fault occurs followed by a permanent current fault. When the first overcurrent fault occurs, the first 100 mV spike on the sense line can be seen. During the tOFF time, this current fault corrects itself. After this time period, a no fault condition is detected and the limited consecutive counter is reset. GATE is reasserted. When the overcurrent fault returns permanently, the limited consecutive retry counter detects seven consecutive faults and the part latches off. UV/OV AS ENABLE PIN Connecting an open collector output to the UV/OV Pin means that a TTL signal can be used to disable the part. In Figure 15, the open collector output connects to EN. Driving the base of the open collector device high enough to cause the UV/OV Pin to be pulled below the undervoltage falling threshold of 0.86 V typical will cause the pass transistor Q1 to be turned off. 0V RDROP R1 VIN GATE Q1 CLOAD VOUT EN UV/OV SENSE RSENSE VEE SENSE R2 TIMER GATE T ADM1070 -48V CH1 100mV BN CH2 5.00V M 500ms Figure 15. UV/OV Used as Enable Input Figure 13. Illustration of the PWM Ratio (tON/tOFF) In this way, the ADM1070 prevents nuisance shutdowns from transient shorts of up to three seconds (typically), but will provide latched shut-down protection from permanently shorted loads. KELVIN SENSE RESISTOR CONNECTION When using a low value sense resistor for high current measurement, the problem of parasitic series resistance can arise. The lead resistance can be a substantial fraction of the rated resistance, making the total resistance a function of lead length. This problem can be avoided by using a Kelvin sense connection. This type of connection separates the current path through the resistor and the voltage drop across the resistor. Figure 14 shows the correct way to connect the sense resistor between the SENSE and VEE Pins of the ADM1070. SENSE RESISTOR CURRENT FLOW FROM LOAD CURRENT FLOW TO -48V BACKPLANE KELVIN SENSE TRACES SENSE VEE ADM1070 Figure 14. Kelvin Sensing with the ADM1070 -14- REV. 0 ADM1070 OUTLINE DIMENSIONS 6-Lead Plastic Surface-Mount Package [SOT-23] (RT-6) Dimensions shown in millimeters 2.90 BSC 6 5 4 1.60 BSC 1 2 3 2.80 BSC PIN 1 0.95 BSC 1.30 1.15 0.90 1.90 BSC 1.45 MAX 0.22 0.08 10 0 0.60 0.45 0.30 0.15 MAX 0.50 0.30 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-178AB REV. 0 -15- -16- C02843-0-9/02(0) PRINTED IN U.S.A. |
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